The present invention relates to magnetic bubble memories, and more particularly to methods for routing of data to and from only non-defective minor loops in bubble memories employing redundant minor loops.
Currently, the most popular architecture for magnetic bubble memories is that in which magnetic bubbles are stored in a plurality of parallel minor loops. In a block replicate bubble memory a serial-parallel bubble propagation path is used to transfer bubbles into parallel minor loops, and a parallel-serial bubble propagation path is used to transfer bubbles from the minor loops.
However, due to a variety of causes, some of the minor loops develop defects during their fabrication. For example, the defects may be due to flaws in the garnet film, which resist bubble propagation. They may also be due to permalloy shorts attributable to photolithographic tolerances, or due to dust and other impurities which enter the memory during its fabrication. As a result, some small percentage of the minor loops, such as five percent or less, typically do not work.
To overcome this problem bubble memories are fabricated with extra or so-called redundant minor loops. Then all defective loops, and any good loops in excess of a design number simply are not used during the write and read operations. Suppose for example, that a bubble memory chip was designed to have 256 fault free minor loops. To achieve this, the memory would be built with some larger number of minor loops, such as 270. Then in most cases, at least 256 loops would be fault free.
The problem then becomes one of devising a method for bypassing the defective loops as information is written into and read from the memory. Suppose that in the preceding example, loops ten and one hundred were defective. Under those conditions, no data could be written into the memory on the tenth and one hundredth clocking pulses out of every 270 clocking pulses. Similarly, during a reading operation, the tenth and one hundredth information bits out of every 270 bits of information that are read from the memory must be ignored.
In the past, such control functions have been performed with the aid of external control circuitry. One common prior art control circuitry includes a read only memory (ROM) that is programmed to indicate which of the loops are defective. Address counters simultaneously address both the ROM and the bubble memory. When the ROM output indicates that the bubble memory location being addressed is defective, corrective action is taken. For a discussion of the ROM approach to mask out defective minor loops, see the book entitled Magnetic-Bubble Memory Technology written by Hsu Chang, pages 35-36, copyright 1978, and published by Marcel Dekker, Inc.
More recently, some bubble memories have included a single extra loop on the chip for storing error map information therein. The user is thus able to read the error map from the memory during system initialization and the error map is thereafter stored in a random access memory (RAM). The RAM is then used in conjunction with control logic to mask out the defective loops during a write or read operation. Published German patent application No. 2804695 filed by Texas Instruments, Inc. is believed to be illustrative of this last mentioned approach.
Both of the above approaches, however, have certain deficiencies. For example, with the ROM approach, each memory system requires unique parts. That is, the ROM for one memory system cannot be used as the ROM in another system because the bubble memory chips in each memory system have different defective minor loops. Furthermore, when a bubble chip in a memory system goes completely bad, due to aging for example, the replacement of the bubble chip also necessitates the replacement of the ROM.
One problem with the prior art bubble memory chips that provide an on chip error may loop is that they include no redundant error map loops. That is, they include only a single error map loop. If that loop is defective, then the entire chip must be discarded. Thus, the production yield of those bubble memories chips is undesirably low. Furthermore, there is a risk when storing the error map in an extra minor loop that the starting and stopping of the drive field will not be precise with regard to 360.degree. of orientation. Because of this, it is possible for magnetic bubbles of the error map to jump between adjacent permalloy propagation elements when they are not supposed to. This so-called data scrambling results in the loss of the error map.
U.S. patent application Ser. No. 3,651 filed Jan. 15, 1979 of Peter K. George now U.S. Pat. No. 4,228,522, assigned to the assignee of the present application, discloses a bubble memory that includes a plurality of minor loops for storing bubbles representative of data therein, and a pair of minor loops for storing bubbles representative of an error map therein. Proper choice of the number of propagation elements enables the error map to be selectively written into and read from only one loop of the pair of error map loops with only a single control line. This design produces a higher chip yield since the chip can still be used even if one error map loop is defective.
Other patents of interest which deal with the problem of masking out defective minor loops in a magnetic bubble memory are U.S. Pat. Nos. 3,909,810; 4,073,012; and 4,090,251.
One problem with the error map approach to handling defective minor loops is that the added control circuitry increases the cost of the bubble memory system. Furthermore, it increases the complexity of the chip design. Also, frequently the bubble memory chips are not interchangeable. In addition, the operating speed of a bubble memory incorporating the error map approach is slower than it would be if the defects were transparent to the user. Consider again the above described example that had 270 total loops of which only 256 were guaranteed to be non-defective. In that memory, a total of 270 revolutions of an external magnetic drive field are required to load one bubble into each of 256 minor loops. Conversely, if the defective loops were transparent to the user, a total of only 256 rotations of the magnetic field would be required to load one bubble into each of the loops.
In co-pending U.S. patent application Ser. No. 968,172, of George Reyling, filed Dec. 11, 1978 and now U.S. Pat. No. 4,233,670, and assigned to the assignee of the present application, there is described a fault transparent magnetic bubble memory in which magnetic bubbles are routed away from defective minor loops by selectively destroying certain permalloy shorting bars to convert double-distance bubble propagation elements to single-distance bubble propagation elements. This is done in both the serial-parallel input and parallel-serial output propagation paths. As a result, the number of rotations of the magnetic drive field that are required to load one bubble into each of 256 non-defective minor loops and to read one bubble from each of these loops can be reduced to 256. The defective minor loops are determined during the fabrication process and preselected ones of the permalloy elements are destroyed using a computer controlled laser beam. The need for error map storage loops, control circuitry for masking out defective minor loops pursuant to the error map, and complex permalloy patterns for handling the on chip propagation and storage of the error map, is eliminated.
Co-pending U.S. patent application Ser. No. 968,172 describes two different techniques for destroying a selected permalloy element. In one method, a laser beam of sufficient power is applied to the element for sufficient duration so that the permalloy element is vaporized and effectively severed at one point. The other method is to heat the permalloy element with the laser beam to a temperature sufficient to substantially degrade the magnetic properties of the element. This will insure that the element acts as a barrier over which magnetic bubbles will not propagate.
Both of the above-described laser beam approaches to destroying selected permalloy elements in order to mask out the defective minor loops have certain drawbacks. It is difficult to clearly and reproduceably severe a permalloy propagation element on a bubble memory chip with a laser beam. Molten material and gas which are generated upon laser beam cutting, tend to escape violently. This can result in rupturing of overlying materials and contamination of adjacent areas with debris. Frequently, the thermal conductivity of the bubble chips varies from one location to the next. A laser blast that might neatly severe a permalloy element in one area of the chip may not accomplish the same objective with regard to an element in another area of the chip. The laser beam can be automatically driven over different elements via computer control. However, it is not possible to continuously vary the intensity of the beam in accordance with the different thermal conductivities of the chip at different locations. Also since laser cuts are made in areas where magnetic bubbles propagate, there is sometimes localized alteration of magnetic properties. This can reduce the operating margins of the chips.
It would be desirable to provide an improved procedure for implementing on-chip error maps that are transparent to the user. An approach that uses a programmable laser for treating preselected control conductors represents one viable solution. Laser treatment of selected control conductors could be confined to regions where bubbles do not propagate. Thus, if there is localized alteration of magnetic properties due to heating, margins will not be reduced as they would with alteration of selected permalloy elements by heating.
U.S. Pat. No. 4,139,906 of Chen, assigned to Rockwell International Corporation, discloses a conductor programmable switching arrangements for controlling the interaction of magnetic bubble domain propagation loops in order to provide a large, serial storage loop which is fault tolerant. The disclosed memory incorporates a plurality of minor loops each including a switch and positioned adjacent a major loop. Under each switch a control conductor is split into narrow and wide segments. Where a specific minor loop is non-defective, the current through the narrow control conductor segment is insufficient to render two included swap or transfer gates active. Under these conductions the minor loop and the major loop are connected in series. Where a specific minor loop is defective, the wide control conductor segment in its switch is broken by etching, laser scribing, or the like. Then the current flowing through the narrow control conductor segment of that switch is sufficient to cause its two transfer gates to be active. This separates the minor loop and the major loop.
The memory of U.S. Pat. No. 4,139,906 just described has some important drawbacks. First of all, it provides only a single long serial shift register. As is well known it is preferable to use architectures other than a single long serial shift register in order to reduce information access time. The most popular of these reduced access time architectures is the so-called block replicate architecture. Another drawback of the memory disclosed in U.S. Pat. No. 4,139,906 is that the disclosed switch whose condition is determined by the severing or non-severing of a control conductor is relatively complex and requires an undue amount of space and power. Two transfer gates are required for each minor loop. Current must continually flow through the unsevered narrow control conductors during propagation to prevent bubbles from entering defective minor loops. Yet another disadvantage of the memory of U.S. Pat. No. 4,139,906 is that the storage capacity of the serial memory varies drastically with the number of defects.
Therefore it would be desirable to incorporate a conductor programmable error map capability into a bubble memory having a fast access architecture such as a block replicate bubble memory.